Structure and fabrication method for capacitors integratible with vertical replacement gate transistors

ABSTRACT

A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region.  
     In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate.  
     In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.

FIELD OF THE INVENTION

[0001] The present invention is directed to semiconductor devicesincorporating junctions of varying conductivity types designed toconduct current and methods of making such devices. More specifically,the present invention relates to a design and a process for fabricatingpolysilicon-nitride-polysilicon, metal-nitride-polysilicon andpolysilicon-oxide-polysilicon capacitors using a fabrication processcompatible with the fabrication of vertical transistors.

BACKGROUND OF THE INVENTION

[0002] Enhancing semiconductor device performance and increasing devicedensity, to increase the number of devices per unit area, continue to beimportant objectives of the semiconductor fabrication industry. Devicedensity is increased by making individual devices smaller and packingdevices more compactly. Also, as the device dimensions (also referred toas feature size or design rules) decrease, the methods for formingdevices and their constituent elements must be adapted. For instance,production line feature sizes are currently in the range of 0.25 micronsto 0.18 microns, with an inexorable trend toward small dimensions.However, as the device dimensions shrink, certain manufacturinglimitations arise, especially with respect to the lithographicprocesses. In fact, current photolithographic processes are nearing thepoint where they are unable to accurately manufacture devices at therequired minimal sizes demanded by today's device users.

[0003] Currently most metal-oxide-semiconductor field effect transistors(MOSFETs) are formed in a lateral configuration with the current flowingparallel to the plane of the substrate or body surface in which thesource and drain regions are formed. As the size of these MOSFET devicesdecreases to achieve increased device density, the fabrication processbecomes increasingly difficult. In particular, the lithographic processfor creating the channel is problematic, as the wavelength of theradiation used to delineate an image in the photolithographic patternapproaches the device dimensions. As applied to lateral MOSFETs, thechannel length is approaching the point where it cannot be preciselycontrolled using these photolithographic techniques.

[0004] Recent advances in packing density have resulted in severalvariations of a vertical MOSFET. In particular, the vertical device isdescribed in Takato, H., et al., “Impact of Surrounding Gates Transistor(SGT) for Ultra-High-Density LSI's, IEEE Transactions on ElectronDevices, Volume 38(3), pp. 573-577 (1991), has been proposed as analternative to the planar MOSFET devices. Recently, there has beendescribed a MOSFET characterized as a vertical replacement gatetransistor. See Hergenrother, et al, “The Vertical-Replacement Gate(VRG) MOSFET: A 50-nm Vertical MOSFET with Lithography-Independent GateLength,” Technical Digest of the International Electron Devices Meeting,p. 75, 1999. Commonly owned U.S. Pat. Nos. 6,027,975 and 6,197,641,which are hereby incorporated by reference, teach certain techniques forthe fabrication of vertical replacement gate (VRG) MOSFETs.

[0005] To fabricate operational circuitry on an integrated circuit (IC),it is also necessary to incorporate passive elements into the ICfabrication process. In particular, capacitors are formed as junctioncapacitors or thin-film capacitors. As is known, the application of areverse bias voltage across a semiconductor junction forces the mobilecarriers to move away from the junction thereby creating a depletionregion. The depletion region acts as the dielectric of a parallel-platecapacitor, with the depletion width representing the distance betweenthe plates. Thus the junction capacitance is a function of the depletionwidth, which is in turn a function of the applied reverse bias and theimpurity concentrations in the immediate vicinity of the junction.Thin-film capacitors, which are a direct miniaturization of conventionalparallel-plate capacitors, are also fabricated for use on integratedcircuits. Like the discrete capacitor, the thin-film capacitor comprisestwo conductive layers separated by a dielectric. One type of thin-filmcapacitor is formed as a metal-oxide-semiconductor capacitor, having ahighly doped bottom plate, silicon dioxide as the dielectric, and ametal top plate. A thin-film capacitor can also be formed with two metallayers forming the top and bottom plates, separated by a dielectric,such as silicon dioxide or silicon nitride. Silicon nitride is preferredsince it offers a higher dielectric constant and can thus provide ahigher capacitance per area. The metal-oxide semiconductor capacitorstructure is the most common because it is readily compatible withconventional integrated circuit processing technology. The capacitanceper unit area of a thin-film capacitor is equal to the ratio of thepermittivity and the dielectric thickness. Although thin-film capacitorsoffer higher capacitance values per unit area and fewer parasiticproblems, they can fail by breakdown of the dielectric when thedielectric voltage rating is exceeded.

SUMMARY OF THE INVENTION

[0006] The present invention teaches a process for fabricatingintegrated circuit structures including both MOSFET devices and variouscapacitor configurations. The process includes forming a first deviceregion, either a source or drain region in a semiconductor substrate. Amultilayer stack of at least three layers is formed over the firstdevice region. The middle layer of the three layers is a sacrificiallayer, which is later be removed and replaced by a gate electrode. Awindow is formed in the three layers followed by the formation of dopedsemiconductor material, i.e., a semiconductor plug, within the window. Asecond device region (either a source region or a drain region) isformed at the upper end of the semiconductor plug. The sacrificial layeris then removed and a gate oxide grown or deposited over the exposedportion of the semiconductor plug. The gate electrode is then formedadjacent the gate oxide. In one embodiment, the gate electrode furtherextends to a region of the substrate beyond the MOSFET device, where itserves as the bottom plate of a capacitor. A dielectric layer is formedover the bottom plate, followed by a top capacitor plate.

[0007] In another embodiment, a capacitor is formed in a second windowformed in the multilayer stack. In particular, the second windowincludes a first conformal conductive layer underlying a dielectriclayer. The second conductive layer (the capacitor top plate) fills theremaining volume in the window. As a result, the three layers in thewindow form a capacitor. It is especially advantageous that theformation of each of these capacitors does not add new mask steps whenapplied to the basic VRG MOSFET process flow. Only mask changes arerequired to fabricate both the planar and the windowed capacitorsaccording to the teachings of the present invention. The teachings ofthe present invention for forming the various capacitor embodiments areapplicable not only to the VRG MOSFET process, but can be applied toother vertical transistor processes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be more easily understood and thefurther advantages and uses thereof more readily apparent, whenconsidered in view of the description of the preferred embodiments andthe following figures in which:

[0009]FIGS. 1A through 1P are cross-sectional views illustrating theprocess steps for fabricating a poly-nitride-poly or ametal-nitride-poly capacitor; and

[0010]FIGS. 2A through 2V are cross-sectional views illustrating theprocess steps for fabricating a poly-oxide-poly capacitor.

[0011] In accordance with common practice, the various describedfeatures are not drawn to scale but are drawn to emphasize specificfeatures relevant to the invention. Reference characters denote likeelements throughout the figures and text.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] The present invention is directed to capacitor structures andassociated fabrication techniques for fabricatingpolysilicon-nitride-polysilicon (PNP), metal-nitride-polysilicon (MNP)and polysilicon-oxide-polysilicon (POP) capacitors using a processsimilar to and compatible with the fabrication of vertical replacementgate metal-oxide-semiconductor field-effect transistors (VRG MOSFETs).In particular, it is desirable to manufacture the capacitors and theVRGs on a single silicon substrate to minimize cost and fabricationcomplexity, with a minimum number of extra steps required to fabricatethe capacitors. The present invention discloses capacitor devices andprocesses for fabricating the capacitors that achieve these goals.

[0013] With regard to the fabrication of transistors and integratedcircuits, the term “major surface” refers to that surface of thesemiconductor layer about which a plurality of transistors arefabricated, e.g., in a planar process. As used herein, the term“vertical” means substantially orthogonal with respect to the majorsurface. Typically, the major surface is along a <100> plane of amonocrystalline silicon substrate on which the field-effect transistordevices are fabricated. The term “vertical transistor” means atransistor with individual semiconductor components vertically orientedwith respect to the major surface so that the current flows verticallyfrom drain to source (electrons flow from source to drain). By way ofexample, for a vertical MOSFET, the source, channel and drain regionsare formed in relatively vertical alignment with respect to the majorsurface.

[0014] Each of FIGS. 1A through 1P and 2A and through 2V illustrate apartial cross-section of an integrated circuit structure during variousstages of fabrication, to configure an exemplary circuit functionaccording to the present invention. From the description, it will becomeapparent how certain capacitors may be configured, alone or incombination with other devices, e.g., bipolar junction transistors,junction field-effect transistors and metal-oxide-semiconductorfield-effect transistors to form an integrated circuit.

[0015] One embodiment of the present invention for fabricating verticalreplacement gate MOSFETs and capacitors on a single silicon substrate isillustrated with reference to FIGS. 1A through 1P. The varioussemiconductor features and regions described therein are preferablycomposed of silicon, but it is known to those skilled in the art thatother embodiments of the invention may be based on other semiconductormaterials (including compound or heterojunction semiconductors) alone orin combination. With references to FIGS. 1A through 1P, fabrication ofthe vertical MOSFET device is illustrated in the left side of thefigures and fabrication of the capacitor is illustrated in the rightside of the Figures. However, it is not necessary for the capacitor andMOSFET devices to be fabricated adjacent each other; the side-by-siderepresentation is utilized solely to illustrate the compatibilitybetween the two processes. The capacitors fabricated according to theteachings of the present invention can be formed anywhere on theintegrated circuit.

[0016] Referring to FIG. 1A, a heavily doped source region 205 is formedalong a major surface 206 in a silicon substrate 200, preferably asubstrate having a <100> crystal orientation. In this embodiment, of avertical MOSFET, the source region of the device is formed in thesilicon substrate and the drain region is formed atop a subsequentlyformed vertical channel, as will be discussed further. In an alternativeembodiment, the drain region is formed in the substrate and the sourceregion is formed atop the vertical channel. The former embodiment is thesubject of this description. However, from this description, one skilledin the art can easily form a device in which the drain region is formedin the silicon substrate and the source region is formed overlying thesubsequently formed vertical channel.

[0017] The depth of the heavily doped source region 205, the dopant type(e.g., n-type or p-type) and the concentration therein are all mattersof design choice. An exemplary source region 205, wherein the dopant isphosphorous (P), arsenic (As), antimony (Sb) or boron (B) has a dopantconcentration in the range of about 1×10¹⁹ atoms/cm³ to about 5×10²⁰atoms/cm³. Depths of the source region 205 and the substrate 200 lessthan about 200 nm are contemplated as suitable.

[0018] In FIG. 1B, five layers of material 210, 211, 215, 216 and 220are formed over the source region 205 in the silicon substrate 200. Theinsulating layer 210 electrically isolates the source region 205 fromwhat will eventually be the overlying gate electrode. Thus, theinsulating layer 210 is composed of a material and has a thickness thatis consistent with this insulating objective. One example of a suitablematerial is doped silicon dioxide. The use of a doped insulating layer210 is advantageous in those embodiments where the insulating layer 210serves as a dopant source, as will be explained below, to formsource/drain extension regions (within the device channel) through asolid phase diffusion process. Examples of a silicon dioxide dopantsource are PSG (phospho-silicate glass, i.e., a phosphorous-dopedsilicon dioxide) and BSG (boro-silicate glass, i.e., a boron-dopedsilicon dioxide), deposited, for example, by plasma-enhanced chemicalvapor deposition (PECVD). Suitable thicknesses for the insulating layer210 are in the range of about 25 nm to about 250 mn.

[0019] An etch stop layer 211 is formed over the insulating layer 210.An etch stop, as is known to those skilled in the art, is designed toprevent an etch expedient from proceeding to an underlying or overlayinglayer or layers. The etch stop therefore, has a significantly greateretch resistance to a selected etchant than the adjacent layer or layersthat are to be removed by the etchant. Specifically in this case, forthe selected etchant, the etch rate of the etch stop layer 211 is muchslower than the etch rate of the overlying layer 215, which, as will bediscussed below, is a sacrificial layer. One skilled in the art is awarethat the selection of an etch stop layer material is determined by theparticular etch expedient used to etch the overlying/underlying layers.In the process of the present invention, where the overlying sacrificiallayer is undoped silicon dioxide (e.g., silicon dioxide formed fromtetraethylene ortho silicate (TEOS)), an etch stop material thateffectively stops etchants for undoped silicon dioxide from penetratingto the layers beneath the etch step layer 211 is selected. Siliconnitride (Si₃N₄) is contemplated as a suitable etch stop material. Thethickness of the etch stop material layer is also dependent on theresistance of the etch stop material to the selected etchant, relativeto the material depth to be removed through the etch process. That is,to be an effective etch stop, the etchant cannot penetrate the etch stoplayer in the time required to remove the desired layer or layers.

[0020] The etch stop layer 211 also functions as an offset spacer, wherethe thickness of the offset spacer is determined by the thickness of theetch stop layer 211. In the context of the present invention, the offsetspacer controls the position of the source/drain extensions relative tothe device channel. Specifically, the presence of the offset spacerlimits the extent to which the source/drain extensions extend under thegate. One skilled in the art is aware that the farther the source/drainextensions extend under the gate, the greater the adverse consequenceson device performance, i.e., the gate/source and gate/drain overlapcapacitance increase. One skilled in the art will also appreciate thatthe offset spacer cannot be so thick as to create a series resistancebetween the source/drain extensions and the inversion layer formed underthe gate, which would also cause unacceptable device performance. Theetch stop layer 211 performs the offset spacer function by its presencebetween the insulating layer 210 and the sacrificial layer 215 when theinsulating layer 210 serves as a dopant source. As the dopants diffusefrom the insulating layer 210, the degree of overlap between thesource/drain extension and the gate can be controlled through thethickness of the etch stop layer 211 together with control over thedopant diffusion rates.

[0021] A sacrificial layer 215 is formed over the etch stop layer 211.The material of the sacrificial layer 215 has a significantly differentetch resistance to the selected etchant than the etch stop layer 211.Specifically, for the selected etchant, the etch rate of the sacrificiallayer 215 is much higher than the etch rate of the etch stop layer 211.The thickness of the sacrificial layer 215 is selected to correspond tothe gate length of the final device, as the sacrificial layer 215 willbe removed and the gate of the device formed in the vacated space.Silicon dioxide, formed through a TEOS process, is an example of asuitable semiconductor material for the sacrificial layer 215.

[0022] An etch stop layer 216 is formed over the sacrificial layer 215.The etch stop layer 216 serves the same functions as the etch stop layer211. Therefore, the considerations that govern the selection of thematerial and thickness for the etch stop layer 211 also govern theselection of the material and thickness for the etch stop layer 216.

[0023] An insulating layer 220 is formed over the etch stop layer 216.It is advantageous if the insulating layer 220 has the same etch rate(in the selected etchant) as the insulating layer 210. In fact from thestandpoint of processing efficiency, it is advantageous if the materialof the insulating layer 210 is the same as the material of theinsulating layer 220. In the embodiment where the insulating layer 220also serves as a dopant source, the insulating layer 220 is PSG or BSG.

[0024] Referring to FIG. 1C, an opening, trench or window 225 is etchedthrough the insulating layer 210, the etch stop layer 211, thesacrificial layer 215, the etch stop layer 216 and the insulating layer220, downwardly to the source region 205. The window horizontaldimension is determined by the desired device performancecharacteristics, the size constraints for the device under fabrication,and the limitations of the lithographic process utilized to form thewindow 225. The length of the window 225 i.e., the length beingorthogonal to both the horizontal and vertical dimensions in the FIG. 1Ccross-section, is largely a matter of design choice. For a givenhorizontal dimension, the current capacity of the channel to be formedlater in the window 225 increases with increasing window length. Thewindow 225 is then subjected to a chemical cleaning process, (e.g., RCAor piranha clean). The piranha process utilizes a sulfuric acid andhydrogen peroxide solution to clean the silicon at the bottom of thewindow 225. As a result of this cleaning step, small portions of theinsulating layers 210 and 220 forming a boundary with the window 225 areremoved. The indentations created are illustrated in FIG. 1D. As shown,the sacrificial layer 215 and the etch stop layers 211 and 216 extendbeyond the edge of the insulating layers 210 and 220.

[0025] Referring to FIG. 1E, with the source region 205 exposed by theetching process that created the window 225, monocrystalline silicon cannow be epitaxially grown from the source region 205 at the bottom of thewindow 225 to form-device quality crystalline semiconductor material230, including a top portion 221, in the window 225. The crystallinesemiconductor material 230 is suitable for serving as a channel of thedevice and for forming source/drain extension regions above and belowthe channel region. The crystalline semiconductor material 230 may alsobe formed by depositing an amorphous or polycrystalline material andthen re-crystallizing the material, e.g., by a conventional furnaceanneal or a laser anneal.

[0026] The crystalline semiconductor material 230 formed in the window225 must be doped to form the device channel, as well as the source anddrain extensions. Dopants of one type (i.e., n-type or p-type) areintroduced into the crystalline semiconductor material 230 to formsource and drain extensions and dopants of the opposite conductivitytype are introduced to form the channel. A variety of techniques to dopethe crystalline semiconductor material 230 are contemplated as suitable.In-situ doping of the crystalline semiconductor material 230 duringformation or implantation of dopants into the crystalline semiconductormaterial 230 after formation are contemplated as suitable processes toform the channel.

[0027] One skilled in the art is familiar with the manner in whichdopants are introduced in situ as a layer of material is formed viachemical vapor deposition, and such techniques are not described indetail herein. Generally, the dopants are introduced into the atmosphereat the appropriate point in the material deposition process so that thedopants are present in the desired location in the crystallinesemiconductor material 230 and at the desired concentration. Appropriatedopant gases include phosphine and diborane. In another embodiment,channel dopants are implanted in the crystalline semiconductor material230 after formation.

[0028] To form the bottom source/drain extensions, dopants can bediffused from the source region 205 into the bottom of the crystallinesemiconductor material 230. An alternate technique for forming thesource/drain extensions is diffusion of the dopants from the insulatinglayers 210 and 220, when those layers are formed of PSG or BSG materialsas suggested above. Generally, in this solid phase diffusion process, adoped (e.g., with arsenic, phosphorous or boron) oxide (e.g., silicondioxide) serves as the dopant source. At elevated temperatures, thedopant is driven from the doped oxide to the adjacent undoped (orlightly doped) regions. In this application, the dopant is driven intothe crystalline semiconductor material 230. This technique isadvantageous because the doped area, that is the source/drainextensions, are defined by the interface between the crystallinesemiconductor material 230 and the insulating layers 210 and 220 thatserve as the dopant sources. This technique allows the formation ofself-aligned source/drain extensions (i.e. the source drain extensionsare aligned with the gate). Examples of solid state diffusion techniquesare described in Ono, M., et al, “Sub-50 nm Gate Length N-MOSFETS with10 nm Phosphorus Source and Drain Junctions,” IEDM93, pp. 119-122 (1993)and Saito, M., et al., “An SPDD D-MOSFET Structure Suitable for 0.1 andSub 0.1 Micron Channel Length and Its Electrical Characteristics,”IEDM92, pp. 897-900 (1992), which are hereby incorporated by reference.The dopant concentration in the source/drain extensions 232 and 233 istypically about at least 1×10¹⁹/cm³, with dopant concentrations of about5×10¹⁹/cm³ contemplated as advantageous. Using this solid phaseddiffusion technique, very shallow source/drain extensions 232 and 233are obtainable. The source/drain extensions 232 and 233 are shown aspenetrating into the crystalline semiconductor material 230, preferablyless than one half the width of the crystalline semiconductor material230. Limiting the dopant penetrations in this manner avoids overlap ofthe doped regions from opposite sides of the crystalline semiconductormaterial 230. Also, the distance that the source/drain extensions 232and 233 extend under the gate 265 is preferably limited to less thanone-fourth of the gate length. As is know to those skilled in the art,the dopants in the source/drain extensions 232 and 233 are of theopposite type from the dopants in the channel of the crystallinesemiconductor material 230.

[0029] Preferably, after the crystalline semiconductor material 230 isdoped, the device is not subjected to conditions that will significantlyaffect the distribution of the dopants in the crystalline semiconductormaterial 230. Consequently, with this approach after this step thesubstrate will not be exposed to temperatures that exceed 1100° C. Infact, it is advantageous if the substrate is not exposed to temperaturesin excess of 1000° C. after this point in the process. In certainembodiments, the substrate is not exposed to temperatures that exceed900° C. for prolonged periods of time (e.g. in excess of severalminutes). However, the substrate can be subjected to rapid thermalannealing (at temperatures of about 1000° C.) without adverselyaffecting the distribution of the dopants in the crystallinesemiconductor material 230.

[0030] Next a conformal drain layer 235 is formed over the insulatinglayer 220 and the top portion 231. The drain layer 235 provides aself-aligned top contact (the drain contact in this embodiment). Oneexample of the suitable material for the drain layer 235 is dopedpolycrystalline silicon. The selected dopant is opposite in type to thatused to form the device channel. The concentration of the dopant isgreater than about 1×10²⁰ atoms/cm³.

[0031] As further illustrated in FIG. 1F, a conformal layer 236 isdeposited over the drain layer 235. The material selected for the layer236 has an etch rate that is significantly slower than the etch rate ofthe sacrificial layer 215, based on the etchant selected to remove thesacrificial layer 215. It is advantageous if the material selected forthe layer 236 is the same as the material of the etch stop layers 211and 216. One example of suitable material is silicon nitride.

[0032] As shown in FIG. 1G, using conventional lithographic techniques,the drain layer 235, the layer 236, and the insulation layer 220 arepatterned (using one or more dry etch steps) so that only those portionsoverlying or adjacent the crystalline semiconductor material 230 and thetop portion 231 remain. The etch stop layer 216 serves to prevent theetch expedients from reaching the underlying layers during this process.

[0033] According to another embodiment of the present invention, ratherthan formed as discussed above, the source/drain extensions 232 and 233are formed at this point in the process by solid phase diffusion fromthe doped insulating layers 210 and 220.

[0034] As illustrated in FIG. 1H, a conformal layer 240 is thendeposited over the entire structure. The material for layer 240 isselected to have an etch rate that is significantly slower than the etchrate of the sacrificial layer 215 in the etchant selected to remove thesacrificial layer 215. One example of a suitable material for the layer240 is silicon nitride. The thickness of the layer 240 is selected sothat the remaining portions of the drain layer 235, the layer 236, andthe insulating layer 220 are protected from contact with subsequentetchants.

[0035] The layer 240 is then etched using an anisotropic etch such asdry plasma etch, which also removes portions of the etch stop layer 216and the sacrificial layer 215. As is known to those skilled in the art,an anisotropic etch material etches vertically, but not laterally alongthe surface. Therefore, as shown in FIG. 1I, the only portion of thelayer 240 that remains after the anisotropic etch is that portionlaterally adjacent to the stack of the insulating layer 220 and thedrain layer 235 and the layer 236. As a result of this etch process, aportion of the etch stop layer 216 has been removed and the sacrificiallayer 215 is now exposed.

[0036] The device is then subjected to a wet etch (e.g., an aqueoushydrofluoric acid) or an isotropic dry etch (e.g., an anhydroushydrofluoric acid), for removing the remainder of the sacrificial layer215. The result is illustrated in FIG. 1J. The insulating layer 210 isstill covered by the etch stop layer 211. The remaining portion of theetch stop layer 216 and the layers 236 and 240 encapsulate theinsulating layer 220 and the drain layer 235, so that these latterlayers remain isolated from contact with the etch expedients. Theexposed portion of the crystalline semiconductor material 230corresponds to the thickness of the sacrificial layer 215 and definesthe physical channel length of the device.

[0037] Referring to FIG. 1K, a sacrificial layer of silicon dioxide 245is thermally grown or deposited on the exposed surface of thecrystalline semiconductor material 230. A sacrificial silicon dioxidethickness on the order of less than about 10 nm is contemplated assuitable. The sacrificial silicon dioxide 245 is then removed (see FIG.1L) using a conventional isotropic etch (e.g. an aqueous hydrofluoricacid). As a result of the formation and then the removal of thesacrificial silicon dioxide 245, the surface of the crystallinesemiconductor material 230 is smoother and some of the sidewall defectsare removed. The etch stop layers 211 and 216 prevent the removalexpedient from contacting the insulating layers 210 and 220 and thedrain layer 235. This step is not necessarily required for the processof the present invention, but can be executed to remove excess sidewalldefects if present.

[0038] A layer of gate dielectric 250 (also referred to as a gate oxide)is then formed on the exposed portion of the crystalline semiconductormaterial 230. Suitable dielectric materials include, for example,silicon dioxide, silicon oxynitride, silicon nitride or metal oxide. Thethickness of the gate dielectric 250 is about 1 nm to about 20 nm. Oneexample of a suitable thickness is 6 nm. In one embodiment, the silicondioxide layer is formed by heating the substrate to a temperature in therange of about 700° C. to about 1000° C. in an oxygen-containingatmosphere. Other expedients for forming the gate dielectric includechemical vapor deposition, jet vapor deposition or atomic layerdeposition, all of which are contemplated as suitable. Conditions forforming the gate dielectric 250 of the desired thickness are well knownto those skilled in the art.

[0039] Referring to FIG. 1N, a gate electrode is formed by depositing agate electrode layer 255 of sufficiently conformal and suitable gatematerial, e.g. a layer of doped amorphous silicon in which the dopant isintroduced in situ. The amorphous silicon is then subsequentlyre-crystallized (by melting) to form polycrystalline silicon. Asmentioned above, this must be accomplished using conditions that do notsignificantly affect the dopant profiles in the crystallinesemiconductor material 230. Other examples of suitable gate electrodematerials include polycrystalline silicon, silicon-germanium andsilicon-germanium-carbon. Metals and metal-containing compounds thathave a suitably low resistivity and are compatible with the gatedielectric material and the other semiconductor processing steps arealso contemplated as suitable gate electrode materials. For CMOS(complementary metal-oxide-semiconductor) applications, it isadvantageous if the gate material has a work function near the middle ofthe band gap of the semiconductor material 230. Examples of such metalsinclude titanium, titanium nitride, tungsten, tungsten silicide,tantalum, tantalum nitride and molybdenum. Suitable expedients forforming the gate electrode material include chemical vapor deposition,electroplating and combinations thereof. The gate electrode layer 255also forms the bottom plate of the subsequently formed capacitor, asdiscussed below.

[0040] A poly-nitride-poly (PNP) or a metal-nitride-poly (MNP) capacitor256 is now formed in a region 257 of the FIG. 1O structure. The gateelectrode layer 255 deposited as described above forms the bottom plateof the capacitor 256. At this point in the process, the VRG MOSFET ismasked off and a silicon nitride layer 258, serving as the capacitordielectric, is formed over the gate electrode layer 255 in the region257. Because silicon nitride has a higher permittivity than silicondioxide, higher capacitance values are achievable for the samedielectric thickness. But it is known that any dielectric material canbe used as the capacitor dielectric. A conductive layer 259 is formedover the silicon nitride layer 258. To form a polyoxide-poly capacitor,the conductive layer 259 is doped polysilicon with a dopingconcentration of approximately at least 1×10²⁰ cm⁻³. To form ametal-nitride-poly capacitor, the conductive layer 259 is formed of ametal material. Following deposition of the conductive layer 259, it isdesirable, but not required, to deposit another nitride layer 260thereover.

[0041] As shown in FIG. 1P, the MOSFET gate electrode layer 255 ispatterned and now referred to as a gate 265. Similarly, the bottomplate, (i.e., the gate electrode layer 255) of the capacitor 256 is alsopatterned and now referred to as a bottom capacitor plate 266. In acircuit configuration where it is required to connect the MOSFET gate tothe capacitor, the gate electrode is not patterned so that theconductive material bridging the MOSFET gate and the bottom capacitorplate remains intact. As shown, if required, a window 267 is etched inthe silicon nitride layer 260, to provide connectivity to the underlyingmetal or polysilicon layer, referred to generally as a top capacitorplate 259. The configuration of the MOSFET gate 265 and the bottomcapacitor plate 266 are largely matters of design choice. However, itshould be noted that the gate 265 surrounds the portion of thecrystalline semiconductor material 230 where the gate oxide has beenformed. In one embodiment, the bottom capacitor plate 266 can beconfigured so that access is provided thereto in the third dimension,which is not shown in FIG. 1P.

[0042] In yet another embodiment of the present invention, at this pointin the process dopants are driven into the crystalline semiconductormaterial 230 by solid phase diffusion from the insulating layers 210 and220 to form source/drain extensions 232 and 233 for the MOSFET device.

[0043] In yet another alternative embodiment (not shown) the top portion231 of the crystalline semiconductor material 230 (see FIG. 1E) ispolished back so that the top portion 231 is co-planar with the topsurface of the insulating layer 220. An expedient such as chemicalmechanical polishing is contemplated as suitable and can be accomplishedimmediately following the formation of the crystalline semiconductormaterial 230 shown in FIG. 1E. Polishing back the top portion 231 allowsfor better control of the diffusions from the insulating layer 220 intothe crystalline semiconductor material 230 to form the drain extensions233.

[0044] In yet another embodiment, a thin layer (e.g., a thickness ofabout 25 nm) of undoped silicon dioxide is formed over the source region205. Referring to FIG. 1E, this layer (not shown) acts as a barrier toundesirable solid phase diffusion from the insulating layer 210, (thedopant source), down through the source region 205 and then up into thecrystalline semiconductor material 230.

[0045] It is also feasible to construct a polysilicon-oxide-polysilicon(POP) capacitor in conjunction with the fabrication of vertical MOSFETdevices. The area utilized for the POP capacitor is significantlysmaller than conventional capacitors fabricated on an integratedcircuit. Also, the ratio of the capacitor surface area to the chip areafor a POP capacitor constructed according to the teaching of the presentinvention is generally greater than the same ratio for the MNP or PNPcapacitors described above. Like the vertical replacement gate MOSFETsdescribed herein, the POP capacitor offers a higher circuit density.

[0046] An embodiment of the process for fabricating the VRG MOSFETs andthe polysilicon-oxide-polysilicon capacitors is illustrated withreference to FIGS. 2A through 2V. The various semiconductor features andregions described therein are preferably composed of silicon, but it isknown to those skilled in the art that other embodiments of theinvention may be based on other semiconductor materials (includingcompound or heterojunction semiconductors) alone or in combination. Withreferences to FIGS. 2A through 2V, fabrication of the vertical MOSFETdevice is illustrated in the left portion of the figures and fabricationof the capacitor is illustrated in the right portion of the Figures,although the claims of the present invention are not limited to theformation of a MOSFET device adjacent a POP capacitor.

[0047] Referring to FIG. 2A, a heavily doped source region 305 is formedalong a major surface 306 in a silicon substrate 300, preferably asubstrate having a <100> crystal orientation. In this embodiment, of avertical MOSFET, the source region of the device is formed in thesilicon substrate and the drain region is formed atop a subsequentlyformed vertical channel, as will be discussed further hereinbelow. In analternative embodiment, the drain region is formed in the substrate andthe source region is formed atop the vertical channel. The formerembodiment is the subject of this description. However, from thisdescription, one skilled in the art can easily form a device in whichthe drain region is formed in the silicon substrate and the sourceregion is formed overlying the subsequently formed vertical channel.

[0048] The depth of the heavily doped source region 305, theconcentration of the dopant therein and the type of dopant (e.g., n-typeor p-type) are all matters of design choice. An exemplary source region305, wherein the dopant is phosphorous (P), arsenic (As), antimony (Sb)or boron (B) has a dopant concentration in the range of about 1×10¹⁹atoms/cm³ to about 5×10²⁰ atoms/cm³. Depths of the source region 305 andthe substrate 300 less than about 300 nm are contemplated as suitable.

[0049] In FIG. 2B, five layers of material 310, 311, 315, 316 and 320are formed over the source region 305 in the silicon substrate 300. Theinsulating layer 310 electrically isolates the source region 305 fromwhat will eventually be the overlying gate electrode. Thus, theinsulating layer 310 is composed of a material and has a thickness thatis consistent with this insulating objective. Examples of suitablematerials include doped silicon dioxide. The use of doped insulatinglayer is advantageous because in certain embodiments, the insulatinglayer 310 serves as a dopant source, as will be explained furtherhereinbelow to form source/drain extension regions within the channelregion of the device through a solid phase diffusion process. Oneexample of a silicon oxide doping source is PSG (phosphosilicate glass,i.e., a phosphorous-doped silicon oxide) or BSG (boro-silicate glass,i.e., a boron-doped silicon oxide). One skilled in the art is aware ofsuitable expedients for forming a layer of PSG or BSG on a substrate,e.g., plasma-enhanced chemical vapor deposition (PECVD). Suitablethicknesses for the insulating layer 310 are in the range of about 25 nmto about 350 nm.

[0050] An etch stop layer 311 is formed over the insulating layer 310.An etch stop, as is known to those skilled in the art, is designed toprevent an etch expedient from proceeding to an underlying or overlayinglayer or layers. The etch stop therefore, has a significantly greateretch resistance to a selected etchant than the adjacent layer or layersthat are to be removed. Specifically in this case, for the selectedetchant, the etch rate of the etch stop layer 311 is much slower thanthe etch rate of the overlying layer 315, which, as discussed below, isa sacrificial layer. One skilled in the art is aware that the selectionof the material for an etch stop layer is determined by the particularetch expedient used to etch the overlying/underlying layers. In theprocess of the present invention, wherein the overlying layer is undopedsilicon dioxide (e.g., silicon dioxide formed from tetraethylene orthosilicate (TEOS)), an etch stop material that effectively stops etchantsfor undoped silicon dioxide from penetrating to the layers beneath theetch stop layer 311 is selected. Silicon nitride (Si₃N₄) is contemplatedas a suitable etch stop material. The thickness of the etch stopmaterial layer is also dependent on the resistance of the etch stopmaterial to the selected etchant, relative to the material depth to beremoved through the etch process. That is, to be an effective etch stop,the etchant cannot penetrate the etch stop layer in the time required toperform the etching of the layer to be removed.

[0051] The etch stop layer 311 also functions as an offset spacer, wherethe thickness of the offset spacer is determined by the thickness of theetch stop layer 311. In the context of the present invention, the offsetspacer controls the position of the junction of the source/drainextensions and the channel, relative to the gate of the device.Specifically, the presence of the offset spacer prevents thesource/drain extensions from extending as far under the gate as theyotherwise would extend if the offset spacer was not present. One skilledin the art is aware that the farther the source/drain extensions extendunder the gate, the greater probability of adverse consequences ondevice performance, i.e., the gate/source and gate/drain overlapcapacitances increase. One skilled in the art will also appreciate thatthe offset spacer cannot be so thick so as to create a series resistancebetween the source/drain extensions and the inversion layer formed inthe channel under the gate, as such a series would also causeunacceptable device performance. The etch stop layer 311 performs theoffset spacer function by its presence between the insulating layer 310and the sacrificial layer 315 when the insulating layer 310 serves as asource for dopants. For a given vertical diffusion distance by thedopants from the insulating layer 310, the degree of overlap between thesource/drain extension and the gate can be controlled precisely throughthe thickness of the etch stop layer 311, together with control over thedopant diffusion rates.

[0052] A sacrificial layer 315 is formed over the etch stop layer 311.The material of the sacrificial layer 315 has a significantly differentetch resistance to the selected etchant than the etch stop layer 311.Specifically, for the selected etchant, the etch rate of the sacrificiallayer 315 is much higher than the etch rate of the etch stop layer 311.The thickness of the sacrificial layer 315 is selected to correspond tothe gate length of the final device, as the sacrificial layer 315 willbe removed and the gate of the device formed in the vacated space.Silicon dioxide is an example of a suitable material for the sacrificiallayer 315. The sacrificial layer 315 can be formed through a TEOSprocess.

[0053] An etch stop layer 316 is formed over the sacrificial layer 315.The etch stop layer 316 serves the same function as the etch stop layer311. Therefore, the considerations that govern the selection of thematerial and thickness for the etch stop layer 311 also govern theselection of the material and thickness for the etch stop layer 316.

[0054] An insulating layer 320 is formed over the etch stop layer 316.It is advantageous if the insulating layer 320 has the same etch rate(in the selected etchant) as the insulating layer 310. In fact from thestandpoint of processing efficiency, it is advantageous if the materialof the insulating layer 310 is the same as the material of theinsulating layer 320. In the embodiment where the insulating layer 320also serves as a dopant source, the insulating layer 320 is PSG or BSG.

[0055] Referring to FIG. 2C, openings, windows or trenches 325 and 326are etched through the insulating layer 310, the etch stop layer 311,the sacrificial layer 315, the etch stop layer 316 and the insulatinglayer 320, downwardly to the source region 305. The window horizontaldimension in the FIG. 2C cross-section is determined by the desireddevice performance characteristics, the size constraints for the deviceunder fabrication and the limitations of the lithographic processutilized to form the windows 325 and 326. The length of the windows 325and 326, i.e., the length being orthogonal to both the horizontal andvertical dimensions in the FIG. 2C cross-section, is largely a matter ofdesign choice. For a given horizontal dimension, the current capacity ofthe channel to be formed later in the window 325, increases withincreasing window length. The dimensions of the window 326 aredetermined by the desired capacitance value.

[0056] The windows 325 and 326 are then subjected to a chemical cleaningprocess, (e.g., RCA or piranha-clean) to clean the silicon at the bottomof the windows 325 and 326. As a result of this cleaning step, smallportions of the insulating layers 310 and 320 forming a boundary withthe windows 325 and 326 are removed. The indentations created areillustrated in FIG. 2D. Thus as shown, the sacrificial layer 315 and theetch stop layers 311 and 316 extend beyond the edge of the insulatinglayers 310 and 320.

[0057] Referring to FIG. 2E, a TEOS layer 327 is deposited over theentire structure. The capacitor region is masked off and the TEOS layer327 removed (e.g. by conventional etching) from the MOSFET region shownin the left side of the structure.

[0058] As shown in FIG. 2F, the window 325 is filled with a crystallinesemiconductor material 330 (e.g., silicon) including a top portion 331.Other examples of crystalline semiconductor materials that can beutilized includes silicongermanium and silicon-germanium-carbon. Thecrystalline semiconductor material 330 may be formed in an undoped orlightly doped state, with completion of the doping process occurringlater. Techniques for forming crystalline semiconductor material in awindow are well known to one skilled in the art. For example, thecrystalline semiconductor material can be formed in the window 325 byepitaxial growth from the source region 305 to form device-qualitysilicon material. In another embodiment, amorphous silicon can bedeposited over the entire substrate 300 and all but the crystallinesemiconductor material 330 and a top portion 331 is removed. Theamorphous semiconductor material is then annealed to re-crystallize it.In yet another embodiment the top portion 331 is removed bychemical/mechanical polishing of the exposed surface immediately afterformation of the crystalline semiconductor material.

[0059] The crystalline semiconductor material 330 formed in the window325 must be doped to form the device channel, as well as the source anddrain extensions. Dopants of one type (i.e., n-type or p-type) areintroduced into the crystalline semiconductor material 330 to form thechannel. A variety of techniques to dope the crystalline semiconductormaterial 330 are contemplated as suitable. In-situ doping of thecrystalline semiconductor material 330 during formation or implantationof dopants into the crystalline semiconductor material 330 afterformation, are contemplated as suitable processes. Dopants can bediffused from the source region 335 into the bottom of the crystallinesemiconductor material 330 to form the source/drain extensions or theycan be formed through solid phase diffusion from an adjacent dopedlayer, such as the doped insulating layers 310 and 320. As discussedabove, the solid phase diffusion step can be executed at severaldifferent points in the fabrication process according to the presentinvention.

[0060] Preferably, after the crystalline semiconductor material 330 isdoped and the dopants distributed therein in the desired manner, thedevice should not be subjected to conditions that can significantlyaffect the dopant distribution in the crystalline semiconductor material330. Consequently, with this approach after this step, the substrate isnot exposed to temperatures that exceed 1100° C. In fact, it isadvantageous if the substrate will not be exposed to temperatures inexcess of 1000° C. after this point in the process. In certainembodiments, the substrate is not exposed to temperatures that exceed900° C. for prolonged periods of time (e.g. in excess of severalminutes). However, the substrate can be subjected to rapid thermalannealing (at temperatures of about 1000° C.) without adverselyaffecting the distribution of the dopants in the crystallinesemiconductor material 330.

[0061] The next several fabrication steps focus on fabrication of thePOP capacitor. However, it is known by those skilled in the art thatthese fabrication steps can be inserted at other points in the VRGfabrication process. The TEOS layer 327 is removed by masking andetching and, as shown in FIG. 2G, a doped polysilicon layer 332 isformed over the structure, including in the window 326. In the region ofthe MOSFET, the doped polysilicon will form either a source or a drainregion for the device; in the region of the POP capacitor, thepolysilicon layer 332 forms one plate of the capacitor. More generally,the layer 332 must be conductive and thus, a metal or metal-containingmaterial may be used in lieu of doped polysilicon for the material ofthe layer 332.

[0062] In the fabrication step represented in FIG. 2H, a layer ofsilicon dioxide 333 is conformally deposited over the polycrystallinelayer 332. Referring to FIG. 2I, a doped polysilicon layer 334 isdeposited over the entire structure, including filling the remainingvoid in the capacitor window 326. After a chemical-mechanical polishingstep, the structure appears as in FIG. 2J, with the oxide layer 333disposed between the polysilicon layers 332 and 334, forming apolysilicon-oxide-polysilicon (POP) capacitor in the window 326. At thispoint, the crystalline semiconductor material 330 for the MOSFET remainsin the window 325.

[0063] The MOSFET is masked, and as shown in FIG. 2K, a layer of siliconnitride 335 is deposited over the capacitor window 326 to isolate thePOP capacitor from additional fabrication steps that could short thepolysilicon layers 332 and 334. Vias will be formed later in the siliconnitride layer 335 to access the capacitor plates. The polysilicon layer331, forming the second plate of the POP capacitor may also be accessedin the third dimension, outside the plane of the FIG. 2K cross-section.Because the POP capacitor is created in a trench of the semiconductorsubstrate 300, the ratio of the surface area of the capacitor to thechip area occupied by the capacitor is much greater than this ratio forthe MNP or PNP capacitors discussed above and for the prior artintegrated circuit capacitors. Thus, in terms of area utilization, thePOP capacitor is a more efficient device.

[0064] At this point in the exemplary fabrication process, processingreturns to the VRG MOSFET device, beginning with FIG. 2L. The POPcapacitor is masked such that it is unaffected by the following VRGMOSFET process steps. A conformal drain layer 336 is formed over theinsulating layer 320. The drain layer 336 provides a self-aligned topcontact (the drain contact in this embodiment). One example of thesuitable material for the drain layer 336 is doped polycrystallinesilicon. The selected dopant is opposite in type to that used to dopethe silicon channel. The concentration of the dopant in the drain layer336 is greater than about 1×10²⁰ atoms/cm³.

[0065] As further illustrated in FIG. 2L, a conformal layer 337 isdeposited over the drain layer 336. The material selected for the layer337 has an etch rate that is significantly slower than the etch rate ofthe sacrificial layer 315, based on the etchant selected to remove thesacrificial layer 315. It is advantageous if the material selected forthe layer 337 is the same as the material of the etch stop layers 311and 316. One example of suitable material is silicon nitride.

[0066] As shown in FIG. 2M, using conventional lithographic techniquesthe drain layer 336, the layer 337, and the insulation layer 320 arepatterned (using one or more dry etch steps) so that only those portionsoverlying or adjacent the crystalline semiconductor material 330 remain.

[0067] In one embodiment, the solid phase diffusion step is performed atthis point in the process to form the source/drain extensions 332 and333.

[0068] As illustrated in FIG. 2N, a conformal layer 340 is thendeposited over the MOSFET region of the structure. The material forlayer 340 is selected to have an etch rate that is significantly slowerthan the etch rate of the sacrificial layer 315, in the etchant selectedto remove the sacrificial layer 315. One example of a suitable materialfor the layer 340 is silicon nitride. The thickness of the layer 340 isselected so that the remaining portions of the drain layer 336, thelayer 337 and the insulating layer 320 are protected from contact withsubsequent etchants.

[0069] The layer 340 is then etched using an anisotropic etch such asdry plasma etch, which also removes a portion of the etch stop layer316. As is known to those skilled in the art, an anisotropic etchmaterial etches vertically, but not laterally along the surface. Asshown in FIG. 20, the only portion of the layer 340 that remains afterthe anisotropic etch is that portion laterally adjacent to the stack ofthe insulating layer 320 and the drain layer 336 and the layer 337. Thesacrificial layer 315 is now exposed and also reduced somewhat in thevertical dimension.

[0070] The mask is now removed from the POP capacitor region and theentire substrate is subjected to a wet etch (e.g., an aqueoushydrofluoric acid) or an isotropic dry etch (e.g., an anhydroushydrofluoric acid), which removes the remaining portion of thesacrificial layer 315 in both the MOSFET region and in the POP capacitorregion. The result is illustrated in FIG. 2P. The insulating layer 310is still covered by the etch stop layer 311, and the exposed portion ofthe etch stop layer 316 and the layers 337 and 340 encapsulate theinsulating layer 320 and the drain layer 336, so that these layersremain isolated from contact with subsequent etch expedients. Also theetch stop layer 316 protects the overlying insulator layer 320 in thePOP capacitor region. The exposed portion of the crystallinesemiconductor material 330 corresponds to the thickness of thesacrificial layer 315 and defines the physical channel length of theMOSFET device.

[0071] The POP capacitor region is masked again and as shown in FIG. 2Q,a sacrificial layer of thermal silicon dioxide 345 is grown on theexposed surface of the crystalline semiconductor material 330 in theMOSFET region. A sacrificial silicon dioxide thickness on the order ofless than about 10 nm is contemplated as suitable. The sacrificialsilicon dioxide 345 is then removed (see FIG. 2R) using a conventionalisotropic etch (e.g. an aqueous hydrofluoric acid). As a result of theformation and then the removal of the sacrificial silicon dioxide 345,the surface of the crystalline semiconductor material 330 is smootherand some of the side wall defects are removed. This step is not requiredaccording to the present invention, but may be advantageous if there areexcessive defects in the crystalline semiconductor material 330. Theetch stop layers 311 and 316 prevent the expedient from contacting theinsulating layers 310 and 320 and the drain layer 336 during thisprocess step.

[0072] As shown in FIG. 2S, a layer of gate dielectric 350 (or gateoxide) is formed on the exposed portion of the crystalline semiconductormaterial 330. Suitable dielectric materials include, for example,silicon dioxide, silicon oxynitride, silicon nitride or metal oxide. Thethickness of the gate dielectric 350 is about 1 nm to about 30 nm. Oneexample of a suitable thickness is 6 nm. In one embodiment, the silicondioxide layer is formed by heating the substrate to a temperature in arange of about 700° C. to about 1000° C. in an oxygen-containingatmosphere. Other expedients for forming the gate dielectric includechemical vapor deposition, jet vapor deposition or atomic layerdeposition, all of which are contemplated as suitable. Conditions forforming the gate dielectric 350 of the desired thickness are well knownto those skilled in the art.

[0073] Referring to FIG. 2T, a gate electrode is formed by depositing agate electrode layer 355 of sufficiently conformal and suitable gatematerial, e.g., a layer of doped amorphous silicon in which the dopantis introduced in situ and then subsequently re-crystallized to formpolycrystalline silicon. As mentioned above, this must be accomplishedusing conditions that do not significantly affect the dopant profiles ofthe dopants in the crystalline semiconductor material 330. Otherexamples of suitable gate electrode materials include polycrystallinesilicon, silicon-germanium and silicon-germanium-carbon. Metals andmetal-containing compounds that have a suitably low resistivity and arecompatible with the gate dielectric material and the other semiconductorprocessing steps, are also contemplated as suitable gate electrodematerials. For CMOS applications, it is advantageous if the gatematerial has a work function approximately near the middle of the bandgap of the crystalline semiconductor material 330. Examples of suchmetals include titanium, titanium nitride, tungsten, tungsten silicide,tantalum, tantalum nitride and molybdenum. Suitable expedients forforming the gate electrode material include chemical vapor deposition,electroplating and combinations thereof.

[0074] According to the structure illustrated in FIG. 2T, the MOSFETgate is connected to one plate of the POP capacitor by way of the gateelectrode layer 355. Although this may be desirable in some circuitconfigurations, in those where it is not, an insulative layer, forexample a silicon dioxide trench, may be formed to isolate that portionof the gate electrode layer 355 adjacent the polysilicon layer 332 ofthe POP capacitor from that adjacent the gate dielectric 350 of theMOSFET device. Such a trench 351 is illustrated in FIG. 2T. Thoseskilled in the art are familiar with the process for forming such atrench. Alternatively, the segment of the gate electrode layer bridgingthe MOSFET gate and the POP capacitor plate can be removed by patterningand etching.

[0075] Referring to FIG. 2U, the gate electrode layer 355 is patterned(which is a matter of design choice) to form a gate 365 of the MOSFETdevice. The gate electrode layer 355 in the POP capacitor region bearsreference character 366. The gate 365 surrounds the crystallinesemiconductor material 330 and the gate oxide 350 formed thereon. Awindow 379 is etched in the capacitor nitride layer 335 to access thepolysilicon, which serves as one capacitor plate. The polysilicon layer382, forming the other capacitor plate, is accessed by a via 371 formedin both silicon nitride layers 316 and 335.

[0076]FIG. 2V shows the finished MOSFET and POP capacitor devices. Ifnot executed earlier in the process, the dopants are now driven into thecrystalline semiconductor material 330 by solid phase diffusion from theinsulating layers 310 and 320 to form the source/drain extensions 332and drain.

[0077] In yet another embodiment of the present invention, a thin layer(e.g., a thickness of about 25 nm) of undoped silicon dioxide is formedover the source layer 305. Referring to FIG. 2E, this layer (not shown)acts as a barrier to undesirable solid phase diffusion from theinsulating layer 310, (the dopant source), down through the source layer305 and then up into the crystalline semiconductor material 330.

[0078] An architecture and process have been described for providingvarious capacitor structures on an integrated circuit, especially anintegrated circuit comprising one or more vertical replacement gateMOSFETs. While specific applications of the invention have beenillustrated, the principals disclosed herein provide a basis forpracticing the invention in a variety of ways and in a variety ofcircuit structures, including circuit structures formed with GroupIII-IV compounds and other semiconductor materials. Although theexemplary embodiments pertain to vertical replacement gate CMOSFETs,numerous variations are contemplated. These includes structurescomprising vertical bipolar transistor devices, diodes and, moregenerally, diffusion regions in conjunction with the capacitorarchitectures described herein. Still other constructions not expresslyidentified herein do not depart from the scope of the invention, whichis limited only by the claims that follow.

What is claimed is:
 1. A process for fabricating an integrated circuitstructure comprising: forming a first device region selected from thegroup consisting of a source region and a drain region of asemiconductor device in a semiconductor substrate; forming a multilayerstack comprising at least three layers of material over the first deviceregion in the semiconductor substrate, wherein the second layer isinterposed between the first and the third layers, and wherein the firstlayer is adjacent the first device region; forming a window in the atleast three layers of material, wherein the window terminates at thefirst device region formed; forming a doped semiconductor plug in thewindow, wherein the semiconductor plug has a first end and a second end,and wherein the first end is in contact with the first device region;forming a second device region selected from the group consisting of asource region and a drain region in the second end of the semiconductorplug, wherein one of the first and second device regions is a sourceregion and the other is a drain region. removing the second layer,thereby exposing a portion of the semiconductor plug; forming gatedielectric material on the exposed portion of the semiconductor plug;forming a conductive layer comprising a horizontal segment and avertical segment, wherein the vertical segment contacts the gatedielectric material to form a gate of a MOSFET device, and thehorizontal segment forms a first capacitor plate; forming a capacitordielectric layer over the first capacitor plate; and forming a secondcapacitor plate over the capacitor dielectric layer.
 2. The process ofclaim 1 wherein the second layer is removed by etching in an etchant,characterized by a first layer etch rate, a second layer etch rate, anda third layer etch rate, and wherein the second layer etch rate is atleast ten times faster than one of the first layer etch rate and thethird layer etch rate.
 3. The process of claim 1 wherein thesemiconductor plug comprises a doped crystalline semiconductor material,and wherein the dopant is selected from the group consisting of n-typedopants and p-type dopants, and wherein the crystalline semiconductormaterial selected from the group consisting of silicon, silicongermanium, and silicon-germanium-carbon.
 4. The process of claim 1further comprising forming a layer of insulating material over eitherthe first layer of material and the second layer of material, or boththe first and second layers of material, wherein the layer of insulatingmaterial comprises an etch stop layer.
 5. The process of claim 4 whereinthe material of the first and the third layers comprises a dopedinsulating material, and wherein source and drain region extensions areformed within the semiconductor plug by the diffusion of dopants fromthe first and the third layers into the adjacent semiconductor plugmaterial, and wherein the layer of insulating material comprises anoffset spacer for controlling the extent of vertical diffusion ofdopants from the first and the third layers.
 6. The process of claim 1wherein the substrate is selected from the group comprising siliconsubstrates and silicon-on-insulator substrates.
 7. The process of claim1 wherein the conductive material is selected from the group consistingof doped polycrystalline silicon, doped amorphous silicon, doped silicongermanium, doped silicon-germamum-carbon, metals and metal compounds 8.The process of claim 1 further comprising the steps of: forming aninsulating layer over the second capacitor plate; and forming a windowin the insulating layer for accessing the second capacitor plate.
 9. Theprocess of claim 8 wherein the insulating layer is selected from thegroup consisting of silicon nitride and silicon dioxide.
 10. The processof claim 1 wherein the first and the second capacitor plates are formedof a material selected from the group comprising doped polysilicon,metal, and metal compounds.
 11. The process of claim 1 wherein thecapacitor dielectric layer is formed of material selected from the groupcomprising silicon dioxide and silicon nitride.
 12. The process of claim1 further comprising insulating the horizontal and the vertical segmentsof the conductive layer.
 13. The process of claim 12 wherein aninsulative trench insulates the horizontal and vertical segments of theconductive layer.
 14. A process for fabricating an integrated circuitstructure comprising: forming a first device region selected from thegroup consisting of a source region and a drain region of asemiconductor device in a semiconductor substrate; forming a multilayerstack comprising at least three layers of material over the first deviceregion in the semiconductor substrate wherein the second layer isinterposed between the first and the third layers, and wherein the firstlayer is adjacent the first device; forming a first and a second windowin the at least three layers of material, wherein said first and secondwindows terminate at the first device region; forming dopedsemiconductor material in the first window, thereby forming a dopedsemiconductor plug in the at least three layers of material, wherein thedoped semiconductor plug has a first end and a second end, and whereinthe first end is in contact with the first device region; forming asecond device region selected from the group consisting of a sourceregion and a drain region in the second end of the doped semiconductorplug, wherein one of the first and second device regions is a sourceregion and the other is a drain region; removing the second layer,thereby exposing a portion of the doped semiconductor plug; forming gatedielectric material on the exposed portion of the first semiconductorplug; forming a gate in contact with the gate dielectric material;forming a first conductive layer in the second window; forming a firstdielectric layer overlying the first conductive layer in the secondwindow; and forming a second conductive layer over the first dielectriclayer in the second window, such that the first conductive layer, thefirst dielectric layer and the second conductive layer form a capacitor.15. The process of claim 14 wherein the second layer is removed byetching in an etchant, characterized by a first layer etch rate, asecond layer etch rate, and a third layer etch rate, and wherein thesecond layer etch rate is at least ten times faster than one of thefirst layer etch rate and the third layer etch rate.
 16. The process ofclaim 15 wherein the etchant is selected from the group consisting ofisotropic wet etchants and isotropic dry etchants.
 17. The process ofclaim 14 wherein the material of the first layer and the third layer isan electrically insulating material is selected from the groupconsisting of silicon nitride, silicon dioxide, and doped silicondioxide.
 18. The process of claim 14 wherein the material of the firstand the third layers comprises doped silicon dioxide, and wherein theprocess further comprises further doping the doped semiconductor plugwith dopant from the first layer and the third layer to form dopedextension regions in the doped semiconductor plug.
 19. The process ofclaim 18 wherein the dopant type in the doped silicon dioxide isselected from the group consisting of n-type and p-type, and wherein thedopant type is opposite the dopant type in the doped semiconductor plug.20. The process of claim 14 wherein the semiconductor plug materialcomprises a crystalline semiconductor material and is selected from thegroup consisting of silicon, silicon-germanium, andsilicon-germanium-carbon.
 21. The process of claim 14 further comprisingforming an etch stop layer over either the first layer of material orthe second layer of material, or over both the first and the secondlayers of material.
 22. The process of claim 14 further comprisingforming a diffusion barrier layer over the first device region beforethe at least three layers of material are formed thereover.
 23. Theprocess of claim 14 wherein the gate is formed from a material selectedfrom the group consisting of doped polycrystalline silicon, dopedamorphous silicon, doped polycrystalline silicon-germanium, dopedamorphous silicon-germanium, doped polycrystallinesilicon-germanium-carbon, doped amorphous silicon-germanium-carbon,metals and metal-containing compounds.
 24. The process of claim 14wherein the gate comprises a first and second segment, and wherein thefirst segment is formed in a region vacated by removal of the secondlayer in the area of the first window such that the first segment isadjacent the gate dielectric, and wherein the second segment is formedin the region vacated by removal of the second layer in the area of thesecond window such that the second segment is adjacent the firstconductive layer in the second window, such that the gate dielectricmaterial is electrically connected to a plate of the capacitor.
 25. Theprocess of claim 24 further comprising forming an insulative layerbetween the first and the second segments of the gate to isolate thegate dielectric material from the capacitor.
 26. The process of claim 14wherein the first and second conductive layers formed in the secondwindow are formed from a material selected from the group consisting ofdoped polycrystalline silicon, doped amorphous silicon, dopedpolycrystalline silicon-germanium, doped amorphous silicon-germanium,doped polycrystalline silicon-germanium-carbon, doped a morphoussilicon-germanium-carbon, metals and metal containing compounds.
 27. Theprocess of claim 14 wherein the first dielectric layer comprisesmaterial selected from the group consisting of silicon dioxide andsilicon nitride.
 28. An integrated circuit structure comprising: asemiconductor layer having a major surface formed along a plane; a firstdoped region of a first conductivity type in a first area of thesurface; multiple layers over said first doped region, wherein saidmultiple layers have a window therein extending to said first dopedregion; a second doped region of a second conductivity type in thewindow; a third doped region of the first conductivity type over saidsecond doped region; a gate oxide adjacent said second doped region; afirst conductive layer comprising first and second segments, whereinsaid first segment is adjacent said gate oxide, and wherein said secondsegment extends to a second area of the surface; a first dielectriclayer over said second segment; and a second conductive layer over saidfirst dielectric layer.
 29. The integrated circuit structure of claim 28wherein the first doped region is a first source/drain region of aMOSFET, the second doped region is a channel region of the said MOSFET,and the third doped region is a second source/drain region of saidMOSFET.
 30. The integrated circuit structure of claim 29 wherein thefirst segment of the conductive layer comprises a gate of the MOSFET anda bottom plate of a capacitor.
 31. The integrated circuit structure ofclaim 28 further comprising an insulator interposed between the firstand the second segments of the first conductive layer so as toelectrically isolate the first and the second segments.
 32. Theintegrated circuit structure of claim 31 wherein the insulator isselected from the group comprising silicon dioxide, silicon nitride andair.
 33. The integrated circuit structure of claim 31 wherein the firstconductive layer is selected from the group consisting of dopedpolycrystalline silicon, dope amorphous silicon, dopedsilicon-germanium, doped silicon-germanium-carbon, metals and metalcompounds.
 34. The integrated circuit structure of claim 28 wherein thematerial of the first dielectric layer is selected from among silicondioxide and silicon nitride.
 35. The integrated circuit structure ofclaim 28 further comprising a second dielectric layer over the secondconductive layer, wherein the second dielectric layer includes at leastone via therein for providing conductive access to at least one of thesecond segment and the second conductive layer.
 36. An integratedstructure comprising: a semiconductor layer having a major surfaceformed along a plane; a first doped region of a first conductivity typein a first area of the surface; multiple layers over said first dopedregion, wherein said multiple layers have a window therein extending tosaid first doped region; a second doped region of a second conductivitytype in the window; a third doped region of the first conductivity typeover said second doped region; an oxide layer adjacent said second dopedregion; a first portion of a first conductive layer in contact with saidoxide layer; within a second window in a second area of the surface; asecond portion of said first conductive layer relatively conformal withthe interior surface of said second window; a conformal dielectric layerover said second portion of said first conductive layer; and a secondconductive layer over said dielectric layer, such that said secondconductive layer, said first dielectric layer and said second portion ofsaid first conductive layer form a capacitor.
 37. The integrated circuitstructure of claim 36 wherein the first portion of the first conductivelayer comprises a gate of the MOSFET and wherein the second portion ofthe first conductive layer comprises a capacitor plate.
 38. Theintegrated circuit structure of claim 36 wherein the material of thefirst conductive layer is selected from the group consisting of dopedpolycrystalline silicon, dope amorphous silicon, dopedsilicon-germanium, doped silicon-germanium-carbon, metals and metalcompounds.
 39. The integrated circuit structure of claim 36 wherein thematerial comprising the dielectric layer is selected from among silicondioxide and silicon nitride.
 40. The integrated circuit structure ofclaim 36 further comprising an insulator material disposed between thefirst and the second portions of the first conductive layer.